New chip designs already exceed two million devices. The greater the number of devices on a chip the greater the possibility that one or more will fail. This would result in a lower yield driving up the cost of the chips. Redundancy techniques are designed to address this problem. Redundancy techniques are routinely used in large memories to lend a degree of defect tolerance and increase yield. In one approach one or more banks of extra memory are provided so that if one or more banks test as defective, the entire bank can be replaced by an extra one thereby saving the chip and increasing yield. However, in memory design the input and output can be the same. Every bank is accessible to the input and output data. The physical location of each memory cell is not position sensitive: it only need be susceptible to storage and retrieval.
In contrast in cross point switching systems there is position sensitivity: the cross point cell location is dictated by the connection it serves to make. This makes difficult redundancy design for replacing defective point cells in cross point switching systems. Nevertheless one approach that apparently has been used to increase yield is to package a number of cross point switch die in a single package making a single larger cross point switch with a higher yield. But this has shortcomings including: the higher power dissipated in intra-die I/O cells; higher path-dependent skew as a result of some connections needing to span the intra-die space; the need to test multiple die to construct a single large cross point switching system; and the need to discard a relatively large piece of silicon if one of these smaller cross point switches proves non-functional. The efficiency of redundancy in achieving improved yield in cross point switching cores is illustrated in the chart below.
CHART IDo [def/cm{circumflex over ( )}2]21.2RedundancyYld (core)Yld (core)038%56%175%89%293%98%